Search results for "pull-in range"
showing 5 items of 5 documents
Computation of lock-in range for classic PLL with lead-lag filter and impulse signals
2016
For a classic PLL with square waveform signals and lead-lag filter for all possible parameters lock-in range is computed and corresponding diagrams are given. peerReviewed
The Egan problem on the pull-in range of type 2 PLLs
2021
In 1981, famous engineer William F. Egan conjectured that a higher-order type 2 PLL with an infinite hold-in range also has an infinite pull-in range, and supported his conjecture with some third-order PLL implementations. Although it is known that for the second-order type 2 PLLs the hold-in range and the pull-in range are both infinite, the present paper shows that the Egan conjecture may be not valid in general. We provide an implementation of the third-order type 2 PLL, which has an infinite hold-in range and experiences stable oscillations. This implementation and the Egan conjecture naturally pose a problem, which we will call the Egan problem: to determine a class of type 2 PLLs for …
Harmonic balance analysis of pull-in range and oscillatory behavior of third-order type 2 analog PLLs
2020
The most important design parameters of each phase-locked loop (PLL) are the local and global stability properties, and the pull-in range. To extend the pull-in range, engineers often use type 2 PLLs. However, the engineering design relies on approximations which prevent a full exploitation of the benefits of type 2 PLLs. Using an exact mathematical model and relying on a rigorous mathematical thinking this problem is revisited here and the stability and pull-in properties of the third-order type 2 analog PLLs are determined. Both the local and global stability conditions are derived. As a new idea, the harmonic balance method is used to derive the global stability conditions. That approach…
Stability of charge-pump phase-locked loops : the hold-in and pull-in ranges
2020
The problem of design and analysis of synchronization control circuits is a challenging task for many applications: satellite navigation, digital communication, wireless networks, and others. In this article the Charge-Pump Phase-Locked Loop (CP-PLL) electronic circuit, which is used for frequency synthesis and clock generation in computer architectures, is studied. Analysis of CP-PLL is not trivial: full mathematical model, rigorous definitions, and analysis still remain open issues in many respects. This article is devoted to development of a mathematical model, taking into account engineering aspects of the circuit, interpretation of core engineering problems, definition in relation to m…
Hold-in, Pull-in and Lock-in Ranges for Phase-locked Loop with Tangential Characteristic of the Phase Detector
2019
In the present paper the phase-locked loop (PLL), an electric circuit widely used in telecommunications and computer architectures is considered. A new modification of the PLL with tangential phase detector characteristic and active proportionally-integrating (PI) filter is introduced. Hold-in, pull-in and lock-in ranges for given circuit are studied rigorously. It is shown that lock-in range of the new PLL model is infinite, compared to the finite lock-in range of the classical PLL. peerReviewed